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1 ? fn9196.0 isl6455, isl6455a triple output regulator with single synchronous buck and dual ldo the isl6455 is a highly integrated triple output regulator which provides a single chip solution for fpgas and wireless chipset power management. th e device integrates a high efficiency synchronous buck regulator (adjustable) with two ultra low noise ldo regulators (adjustable). either the isl6455 or isl6455a can be selected based on whether 3.3v 10% or 5v 10% is required as an input voltage. the synchronous current mode control pwm regulator with integrated n- and p-channel power mosfet provides adjustable voltages based on external resistor setting. synchronous rectification with internal mosfets is used to achieve higher efficiency and reduced number of external components. operating frequency is typically 750khz allowing the use of smaller inductor and capacitor values. the device can be synchronized to an external clock signal in the range of 500khz to 1mhz. the pg_pwm output indicates loss of regulation on pwm output. the isl6455 also has two ldo adjustable regulators using internal pmos transistors as pass devices. ldo2 features ultra low noise typically below 30v rms to aid vco stability. the en_ldo pin controls ldo1 and ldo2 outputs. the isl6455 also integrates a reset function, which eliminates the need for additiona l reset ic required in wlan and other applications. the ic asserts a reset signal whenever the v in supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after v in has risen above the reset threshold. the pg_ldo output indicates loss of regulation on either of the two ldo outputs. other features include overcurrent protection and thermal shutdown for all the three outputs. high integration and the thin quad flat no-lead (qfn) package makes isl6455 an id eal choice for powering fpgas and small form factor wireless cards such as pcmcia, mini-pci and cardbus-32. features ? fully integrated synchronous buck regulator + dual ldo ? pwm output voltage adjustable. - 0.8v to 2.5v with isl6455 (vin = 3.3v) - 0.8v to 3.3v with isl6455a (vin = 5.0v) ? high output current. . . . . . . . . . . . . . . . . . . . . . . . . 600ma ? dual ldo adjustable options - ldo1, 1.2v to vin-0.3v (3.3vmax). . . . . . . . . . . 300ma - ldo2, 1.2v to vin-0.3v (3.3vmax). . . . . . . . . . . 300ma ? ultra-compact dc/dc converter design ? stable with small ceramic output capacitors and no load ? high conversion efficiency ? low shutdown supply current ? low dropout voltage for ldos - ldo1 . . . . . . . . . . . . . . . . . . 150mv (typical) at 300ma - ldo2 . . . . . . . . . . . . . . . . . . 150mv (typical) at 300ma ? low output voltage noise - <30v rms (typical) for ldo2 (vco supply) ? pg_ldo and pg_pwm (pwm and ldo) outputs ? extensive circuit protection and monitoring features - pwm overvoltage protection - overcurrent protection - shutdown - thermal shutdown ? integrated reset output for microprocessor reset ? proven reference design for total wlan system solution ? qfn package - compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - near chip-scale package footprint improves pcb efficiency and is thinner in profile ? pb-free plus anneal available (rohs compliant) applications ? wlan cards - pcmcia, cardbus32, minipci cards - compact flash cards ? hand-held instruments related literature ? tb363 - guidelines for handling and processing moisture sensitive surface mount devices (smds) ? tb389 - pcb land pattern design and surface mount guidelines for qfn packages ordering information part number* (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6455irz 6455irz -40 to 85 24 ld qfn l24.4x4b isl6455airz 6455airz -40 to 85 24 ld qfn l24.4x4b add ?-tk? or t5k suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet december 21, 2005 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9196.0 december 21, 2005 pinout isl6455, isl6455a (qfn) top view typical application schematic en sync gnd ct vout pgnd lx pvcc vin pg_ldo en_ldo sgnd fb_ldo1 gnd_ldo vout1 vin_ldo vin_ldo pg_pwm 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 789101112 fb_ldo2 cc1 cc2 reset vout2 fb_pwm 11 13 4 22 12120 12 9 6 3 5 17 15 7 8 gnd_ldo vout1 fb_ldo1 14 23 10 2 16 24 19 18 vout en_ldo vout2 gnd pgnd lx pvcc vin sgnd fb_pwm sync cc1 pg_ldo reset ct vin_ldo vin_ldo cc2 fb_ldo2 10 f c7 l1 8.2 h vopwm vout2 vout1 c4 10 f 10 f c3 c2 33nf 3.3v c8 c9 c10 r1 10k r3 10k 3.3v 3.3v 4.7 f c5 c1 10nf 0.1 f 1.0 f 10 f note: all capacitors are ceramic. isl6455 c6 33nf pg_pwm en ra rb rc rd re rf isl6455, isl6455a
3 fn9196.0 december 21, 2005 functional block diagram band gap ref 1.2v thermal shutdown 150c gm + - ldo2 + - gm window ldo1 vin_ldo vin_ldo vout1 cc1 vout2 cc2 control logic ct en reset reset gnd_ldo pg_ldo por por comp. window comp. en_ldo soft- start compensation ea gm 750khz oscillator slope compensation en pwm overcurrent, overvoltage logic power good pwm v out uvlo pwm reference 0.45v gate drive current sense lx pgnd vout vout pg_pwm en sync gnd vin pvcc sgnd fb_pwm fb_ldo1 fb_ldo2 10nf 3.3v 10k vin rtn 10k 10k 3.3v 3.3v 10k r e r f 10f 8.2h 3.3v r a r b 0 10f vout2 33nf 33nf r c r d 0 10f vout1 vin_ldo en isl6455, isl6455a
4 fn9196.0 december 21, 2005 absolute maxi mum ratings (note 1) thermal information supply voltage v in , pv cc , v in _ldo. . . . . . . . gnd -0.3v to +6.0v max continuous output current . . . . . . . . . . . . . . . . . . . . . . 600ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c thermal resistance (typical) ja (c/w) jc (c/w) 24 ld qfn (note 1) . . . . . . . . . . . . . . . 42 6 maximum junction temperature (plastic package) . -55c to 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions unless otherwise noted. v in = v in _ldo = pv cc = 3.3v for isl6455 and 5.0v for the isl6455a, compensation capacitors = 33nf for ldo1 and ldo2. t a = -40c to 85 (note 2), typical values are at t a = 25c. parameter test conditions min typ max units v cc supply vin_pwm supply voltage range isl6455 3.0 3.3 3.6 v isl6455a 4.2 5.0 5.5 v vin_ldo supply voltage range 3.0 - 5.5 v operating supply current (note 3) for isl6455 v in = v in _ldo = pv cc = 3.3v f sw = 750khz, c out = 10 f , i l = 0ma -2.53.1ma operating supply current (note 3) for isl6455a v in = v in _ldo = pv cc = 5.0v f sw = 750khz, c out = 10 f , i l = 0ma -3.54.5ma shutdown supply current isl6455 and isl6455a en = en_ldo = gnd - 5 10 a input bias current (en pin) en = en_ldo = gnd/v in -1.5 1.0 1.5 a vin_pwm uvlo threshold for isl6455 v tr 2.55 2.65 2.71 v v tf 2.51 2.56 2.61 v vin_pwm uvlo threshold for isl6455a v tr 3.94 4.05 4.13 v v tf 3.78 3.89 3.97 v vin_ldo uvlo threshold for isl6455 and isl6455a v tr 2.46 2.64 2.82 v v tf 2.53 2.59 2.66 v thermal shutdown temperature (note 6) rising threshold - 150 - c thermal shutdown hysteresis (note 6) - 20 - c synchronous buck pwm regulator output voltage isl6455 0.8 - 2.5 v isl6455a 0.8 - 3.3 v fb_pwm initial voltage accuracy (note 7) v ref = 0.45v, i out = 3ma, t a = -40c to 85c -0.9 - 0.9 % fb_pwm line regulation i o = 3ma, v in = pv cc = 3.0-3.6v (isl6455) or 4.2-5.5v (6455a) -0.5 - 0.5 % fb_pwm load regulation i o = 3ma to 500ma, v in = pv cc = 3.0-3.6v (isl6455) or 4.2-5.5v (isl6455a) -1.1 - +1.1 % peak output current limit 700ma - 1300 ma pmos r ds(on) i out = 200ma - 170 - m ? nmos r ds(on) i out = 200ma - 50 - m ? isl6455, isl6455a
5 fn9196.0 december 21, 2005 efficiency i out = 200ma, v in = 3.3v, v out = 1.8v - 93 - % soft-start time 4096 clock cycles @ 750khz - 5.5 - ms oscillator oscillator frequency t a = -40c to +85c 620 750 880 khz frequency synchronization range (f sync ) clock signal on sync pin 500 - 1000 khz sync high level input voltage as % of v in 70 - - % sync low level input voltage as % of v in --30% sync input leakage current sync = gnd or v in -1.0 - 1.0 a min duty cycle of external clock signal (note 6) - 20 - % max duty cycle of external clock signal (note 6) - 80 - % pg_pwm rising threshold 1.2ma source /sink, fb_pwm vs 0.45v v ref +5.5 8.0 +10.5 % falling threshold fb_pwm vs 0.45v v ref -10.5 -8.0 -5.5 % leakage current pg_pwm = gnd or v in - 0.01 0.1 a ldo1 specifications output voltage range vin_vldo > 3.0v 1.2 - 2.7 v output voltage range vin_vldo > 3.6v 1.2 - 3.3 v fb_ldo1 voltage accuracy (note 7) i out = 10ma -1.5 - 1.5 % maximum output current (note 6) v in = 3.6v 300 - - ma output current limit (note 6) 350 420 600 ma dropout voltage (note 4) i out = 300ma - 150 300 mv fb_ldo1 line regulation i out = 10ma, vin_ldo = 3.0-5.5v -0.5 - 0.5 %/v fb_ldo1 load regulation i out = 10ma to 300ma -0.5 - 0.5 % output voltage noise (note 6) 10hz < f < 100khz, i out = 10ma c out = 2.2 f-65- v rms c out = 10 f-60- v rms ldo2 specifications output voltage range vin_vldo > 3.0v 1.2 - 2.7 v output voltage range vin_vldo > 3.6v 1.2 - 3.3 v fb_ldo2 voltage accuracy (note 7) i out = 10ma -1.5 - 1.5 % maximum output current (note 6) v in = 3.6v 300 - - ma output current limit (note 6) 350 420 600 ma dropout voltage (note 4) i out = 300ma - 150 300 mv fb_ldo2 line regulation i out = 10ma, vin_ldo = 3.0-5.5v -0.5 - 0.5 %/v fb_ldo2 load regulation i out = 10ma to 300ma -0.5 - 0.5 % output voltage noise (note 6) 10hz < f < 100khz, i out = 10ma c out = 2.2 f-30- v rms c out = 10 f-20- v rms electrical specifications recommended operating conditions unless otherwise noted. v in = v in _ldo = pv cc = 3.3v for isl6455 and 5.0v for the isl6455a, compensation capacitors = 33nf for ldo1 and ldo2. t a = -40c to 85 (note 2), typical values are at t a = 25c. (continued) parameter test conditions min typ max units isl6455, isl6455a
6 fn9196.0 december 21, 2005 enable (en and (en_ldo) en high level input voltage as % of vin 70 - - % en low level input voltage as % of vin - - 30 % reset block specifications reset (reset released) isl6455, isource = 500 a, vin = 2.90v 0.8 x v cc --v reset (reset asserted) isl6455, isink = 1.2ma, vin = 2.50v - - 0.3 v reset rising threshold isl6455 2.71 2.77 2.84 v reset falling threshold isl6455 2.69 2.75 2.81 v reset (reset released) isl6455a, isource = 800 a, vin = 4.70v 0.8 x v cc --v reset (reset asserted) isl6455a, isink = 3.2ma, vin = 4.10v - - 0.4 v reset rising threshold isl6455a 4.19 4.27 4.35 v reset falling threshold isl6455a 4.16 4.24 4.32 v reset threshold hysteresis isl6455 - 20 - mv reset threshold hysteresis isl6455a - 30 - mv reset active timeout period (note 5) c t = 0.01 f-25-ms power good (pg_ldo) minimum input voltage for valid pg_ldo - 1.2 - v pgood threshold (rising) fb_ldo vs 1.184v vref +11 +15 +17 % pgood threshold (falling) -17 -15 -11 % pgood output voltage low i ol = 1.2ma - - 0.4 v pgood output leakage current pg_ldo = gnd or vin - 0.01 0.1 a pwm output overvoltage overvoltage threshold fb_pwm vs 0.45v vref 28 31 34 % notes: 3. specifications at -40c and +85c are guaranteed by 25c test with margin limits. 4. this is the v in current consumed when the device is active but not switching. does not include gate drive current. 5. the dropout voltage is defined as v in - v out , when v out is 50mv below the value of v out for v in = v out + 0.5v. 6. the reset timeout period is linear with ct at the slope of 2.5ms/nf. thus, at 10nf (0.01 f) the reset time is 25ms; at 1000nf (0.1 f) the reset time would be 250ms. 7. guaranteed by design, not production tested. 8. add the external feedback resistor mismatch error to get initial v out accuracy. electrical specifications recommended operating conditions unless otherwise noted. v in = v in _ldo = pv cc = 3.3v for isl6455 and 5.0v for the isl6455a, compensation capacitors = 33nf for ldo1 and ldo2. t a = -40c to 85 (note 2), typical values are at t a = 25c. (continued) parameter test conditions min typ max units isl6455, isl6455a
7 fn9196.0 december 21, 2005 pg_ldo timing diagram v in v uvlo v pg vfb_ldo pg_ldo voltage threshold pg_ldo output output undefined v uvlo v pg rising max +18% falling min -17% output undefined t note: 9. v pg is the minimum input voltage for a valid pg_ldo. t t isl6455, isl6455a
8 fn9196.0 december 21, 2005 pin descriptions pvcc - positive supply for the power (internal fet) stage of the pwm section. sgnd - analog ground for the pwm. all internal control circuits are referenced to this pin. en - the pwm controller is enabled when this pin is high, and disabled when the pin is pulled low. it is a cmos logic- level input (referenced to v in ). v in _ldo - this is the input voltage pin for ldo1 and ldo2. en_ldo - ldo1 and ldo2 are enabled when this pin is high, and disabled when the pin is pulled low. it is a cmos logic-level input (referenced to v in ). ct - timing capacitor pin to set the 25ms minimum pulse width for the reset signal. reset - this pin is the output of the reset supervisory circuit, which monitors vin_pwm. the ic asserts a reset signal whenever the supply voltage drops below a preset threshold. it is kept asserted for a minimum of 25ms after v cc (v in ) has risen above the reset threshold. the output is push-pull. the device will continue to operate until v in drops below the uvlo threshold. when en = low then reset = high and the moment en is made high the reset will pulse low for a period of 25ms minimum (vin > reset threshold). if vin < reset threshold then it will switch low and stay low for a period of 25ms after vin_pwm crosses the reset threshold. pg_ldo - this is a high impedanc e open drain output that provides the status of both ldos . when either of the outputs are out of regulation, pg_ldo goes low. cc1 - this is the compensation capacitor connection for ldo1. connect a 0.033f capacitor from cc1 to gnd_ldo. cc2 - this is the compensation capacitor connection for ldo2. connect a 0.033f capacitor from cc2 to gnd_ldo. v out2 - this pin is the output of ldo2. bypass with a minimum 2.2f, low esr capaci tor to gnd_ldo for stable operation. gnd_ldo - ground pin for ldo1 and ldo2. v out1 - this pin is the output of ldo1. bypass with a minimum 2.2f, low esr capaci tor to gnd_ldo for stable operation. pgnd - power ground for the pwm controller stage. v out - this i/o pin senses the output voltage of the pwm converter for the purpose of detecting the over and undervoltage conditions. pg_pwm - this pin is an active pull-up/pull-down able to source/sink 1ma (min.) at 0.4v from v in /sgnd. this output is high when v out is within 8% (typical). fb_ldo1 and fb_ldo2 - these pins are used to set the ldo output with the proper selecti on of resistors. i.e. ra and rb for ldo1 and rc and rd for ldo2. resistors should be chosen to provide a minimum current of 200a load for each ldo output. lx - the lx pin is the switching node of synchronous buck converter, connected internally at the junction point of the upper mosfet source and lower mosfet drain. connect this pin to the output inductor. v in - this pin is the power supply for the pwm controller stage and must be closely decoupled to ground. sync - this is the external clo ck synchronization input. the device can be synchronized to 500khz to 1mhz switching frequency. if unused then it should be tied to gnd or vcc gnd - tie this pin to the ground plane with a low impedance, shortest possible path. fb_pwm - this is used to set the value of the output voltage of the pwm with external resistors re and rf. functional description the isl6455 is a 3-in-1 mult i-output regulator designed for fpga and wireless chipset power applications. the device integrates a single synchronous buck regulator with dual ldos. the pwm output can be set by choosing appropriate values for re and rf. at a setting of 1.8v the synchronous buck regulator provides for an efficiency greater than 92%. the ldo1 can be set with resistor pair rc and rd. the ldo2 can be set with the resistor pair ra and rb. undervoltage lock-out (uvlo) prevents the converter from turning on when the input voltage is less than 2.6v typical. additional blocks include output overcurrent protection, thermal sensor, pgood detectors, reset function and shutdown logic. synchronous buck regulator the synchronous buck regulator with integrated n- and p-channel power mosfets and external voltage setting resistors provides for adjustable voltages from the pwm. synchronous rectification with internal mosfets is used to achieve higher efficiency and reduced number of external components. operating frequency is typically 750khz allowing the use of smaller inductor and capacitor values. the device can be synchronized to an external clock signal in the range of 500khz to 1mhz. the pg_pwm output indicates loss of regulation on pwm output. the pwm architecture uses a peak current mode control scheme with internal slope comp ensation. at the beginning of each clock cycle, the high side p-channel mosfet is turned on. the current in the inductor ramps up and is isl6455, isl6455a
9 fn9196.0 december 21, 2005 sensed via an internal circuit. the error amplifier sets the threshold for the pwm comparator. the high side switch is turned off when the sensed inductor current reaches this threshold. after a minimum dead time preventing shoot through current, the low side n-channel mosfet will be turned on and the current ramps down again. as the clock cycle is completed, the low side switch will be turned off and the next clock cycle starts. the control loop is internally compensated reducing the amount of external components. the switch current is internally sensed and the maximum peak current limit is 1300ma. synchronization the typical operating frequency for the converter is 750khz if no clock signal is applied to sync pin. it is possible to synchronize the converter to an external clock within a frequency range from 500khz to 1mhz. the device automatically detects the rising edge of the first clock and will synchronize immediately to the external clock. if the clock signal is stopped, the co nverter automatic ally switches back to the internal clock and continues operation without interruption. the switch over will be initiated if no rising edge on the sync pin is detected for a duration of two internal 1.3s clock cycles. soft-start as the en (enable) pin goes high, the soft-start function will generate an internal voltage ramp. this causes the start-up current to slowly rise prev enting output voltage overshoot and high inrush currents. the so ft-start duration is typically 5.5ms with 750khz switching fr equency. when the soft-start is completed, the error amplifie r will be connected directly to the internal voltage reference. the sync input is ignored during soft-start. enable pwm logic low on en pin forces the pwm section into shutdown. in shutdown all the major blo cks of the pwm including power switches, drivers, voltage re ference, and oscillator are turned off. power good (pg_pwm) when chip is enabled, this output is asserted high, when v out is within 8% of vopwm value and active low outside this range. when the pwm is disabled, the output is active low. leave the pg_pwm pin unconnected when not used. pwm overvoltage and overcurrent protection the pwm output current is sampled at the end of each pwm cycle. should it exceed the overcurrent limit, a 4 bit up/down counter counts up two lsb. should it not be in overcurrent the counter counts down one lsb (but the counter will not "rollover" or count below 0000). if >33% of the pwm cycles go into overcurrent, the counter rapidly reaches count 1111 and the pwm output is shut dow n and the soft-start counter is reset. after 16 clocks the pwm output is enabled and the ss cycle is started. if v out exceeds the overvoltage limit for 32 consecutive clock cycles, the pwm output is shut off and the ss counters reset. the chip waits for the output voltage to go below undervoltage (8% below nominal) the goes through two dummy soft-start cycles (pwm disabled for 2 ss cycles = 11ms) and then starts a normal soft-start cycle. pg_ldo pg_ldo is an open drain pulldown nmos output that will sink 1ma at 0.4v maximum. it go es to the active low state if either ldo output is out of re gulation by a value greater than 15%. when the ldo is disabled, the output is active low. ldo regulators each ldo consists of a 1.184v reference, error amplifier, mosfet driver, p-channel pass transistor, dual-mode comparator. the voltage is set by means of two resistors the ra and rb for ldo2 and rc and rd for ldo1. the 1.184v band gap reference is connected to the error amplifier?s inverting input. the error amp lifier compares this reference to the selected feedback voltage and amplifies the difference. the mosfet driver reads the error signal and applies the appropriate drive to the p-channel pass transistor. if the feedback volt age is lower than the reference voltage, the pass transistor gate is pulled lower, allowing more current to pass and increas ing the output voltage. if the feedback voltage is higher then the reference voltage, the pass transistor gate is driven higher, allowing less current to pass to the output. internal p-channel pass transistors both the ldo regulators in isl6455 feature a typical 0.5 ? r ds(on) p-channel mosfet pass transistor. this provides several advantages over similar designs using pnp bipolar pass transistors. the p-channel mosfet requires no base drive, which reduces quiescent current considerably. pnp based regulators waste considerable current in dropout when the pass transistor saturates. they also use high base drive currents under large load s. the isl6455 does not have these drawbacks. integrated reset for ma c/baseband processors the isl6455 includes a microprocessor supervisory block. this block eliminates an extra reset ic and external components needed in wireless chipset applications. this block performs a single function; it asserts a reset signal whenever the vin_pwm supply voltage decreases below a preset threshold, and keeps it asserted for a programmable time period set by the external capacitor ct. uvlo reset threshold is always lower than the reset threshold. this insures that as v in falls, the reset goes low before the ldos and pwm are shut off. isl6455, isl6455a
10 fn9196.0 december 21, 2005 integrator circuitry both isl6455 ldo regulators use external 33nf compensation capacitors for minimizing load and line regulation errors and for lowering output noise. when the output voltage shifts due to varying load current or input voltage, the integrator capacitor voltage is raised or lowered to compensate for the systematic of fset at the error amplifier. compensation is limited to 5% to minimize transient overshoot when the device goes out of dropout, current limit, or thermal shutdown. shutdown driving the en_ldo pin low will put ldo1 and ldo2 into the shutdown mode. driving the en pin low will put the pwm into shutdown mode. pulling the en and en_ldo both pins low simultaneously, puts the isl6455, isl6455a in a shutdown mode, and supply current drops to 15a typical. protection features for the ldos current limit the isl6455 and isl6455a monitor and control the pass transistor?s gate voltage to lim it the output current. the current limit for both ldo1 an d ldo2 is 330ma. the output can be shorted to ground without damaging the part due to the current limit and the rmal protection features. thermal overload protection thermal overload protection limits total power dissipation in the isl6455, isl6455a. when the junction temperature (t j ) exceeds +150c, the thermal sensor sends a signal to the shutdown logic, turning off the pass transistor and allowing the ic to cool. the pass transistor turns on again after the ic?s junction temperature typica lly cools by 20c, resulting in an intermittent output condition during continuous thermal overload. thermal overload prot ection protects the isl6455, isl6455a against fault conditions . for continuous operation, the absolute maximum junction temperature rating of +150c in not to be exceeded. operating region and power dissipation the maximum power dissipation of isl6455 depends on the thermal resistance of the ic package and circuit board, the temperature difference between the die junction and ambient air, and the rate of air flow. the power dissipated in the device is: pt = p1 + p2 + p3, where p1 = i out1 x v out1 x n, n is the efficiency of the pwm p2 = i out2 (v in ? v out2 ) p3 = i out3 (v in - v out3 ) the maximum power dissipation is: p max = (t jmax ? t a )/ ja where t jmax = 150c, t a = ambient temperature, and ja is the thermal resistance from the junction to the surrounding environment. the isl6455, isl6455a package feature an exposed thermal pad on its underside. this pad lowers the thermal resistance of the package by providing a direct heat conduction path from the die to the pc board. additionally, the isl6455 and isl6455a ground (gnd_ldo and pgnd) performs the dual function of providing an electrical connection to system ground and channeling heat away. connect the exposed bottom pad direct to the gnd_ldo ground plane. application information ldo regulator capacitor selection and regulator stability capacitors are required at the isl6455, isl6455a ldo regulators? input and output for stable operation over the entire load range and the full temperature range. use >1f capacitor at the input of ldo regulators, v in _ldo pins. the input capacitor lowers the source impedance of the input supply. larger capacitor values and lower esr provide better psrr and line transient response. the input capacitor must be located at a distance of not more than 0.5 inches from the v in pins of the ic and returned to a clean analog ground. any good quality ceramic capacitor can be used as an input capacitor. the output capacitor must meet the requirements of minimum amount of capacitance and esr for both ldos. the isl6455 is specifically designed to work with small ceramic output capacitors. the output capacitor?s esr affects stability and output noise. use an output capacitor with an esr of 50m ? or less to insure stability and optimum transient response . for stable operation, a ceramic capacitor, with a minimum value of 3.3f, is recommended for v out1 for 300ma output current, and 3.3f is recommended for v out2 at 300ma load current. there is no upper limit to the output capaci tor value. a larger capacitor can reduce noise and improve load transient response, stability and psrr. a higher value output capacitor (10f) is recommended for ldo2 when used to power vco circuitry in wireless chipsets. the output capacitor should be located very close to v out pins to minimize impact of pc board inductances and the other end of the capacitor should be returned to a clean analog ground. pwm regulator component selection inductor selection a 8.2h typical output inductor is used with the isl6455 and a 12h typical with the isl6455a pwm section. values less than this may cause stability problems because of the internal compensation of the regulator. the important parameters of the inductor t hat need to be considered are the current rating of the inductor and the dc resistance of isl6455, isl6455a
11 fn9196.0 december 21, 2005 the inductor. the dc resistance of the inductor will influence directly the efficiency of the c onverter. therefore, an inductor with lowest dc resistance should be selected for highest efficiency. in order to avoid saturation of the inductor, the inductor should be rated at least for the maximum output current plus the inductor ripple current. output capacitor selection for the best performance, a low esr output capacitor is needed. if an output capacitor is selected with an esr value 120m ? , its rms ripple current rating will always meet the application requirements. the rms ripple current is calculated as: the overall output ripple voltage is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charge and discharging the output capacitor: where the highest output voltage ripple occurs at the highest input voltage. input capacitor selection because of the nature of the buck converter having a pulsating input current, a low esr input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. the input capacitor should have a minimum value of 10f and can be increased without any limit for better input voltage filtering. the input capacitor should be rated for the maximum input ripple current calculated as: the worst case rms ripple current occurs at d = 0.5. ceramic capacitors show good performance because of their low esr value, and because they are less sensitive to voltage transients, compared to tantalum capacitors. place the input capacitor as close as possible to the input pin of the ic for be st performance. output voltage setting the equations for the output voltages are given below: the output resistors should be selected so that the minimum output load is about 200 a. layout considerations as for all switching power supplies, the layout is an important step in the design of isl64 55, isl6455a based power supply due to the high switching frequency and low noise ldo implementations. allocate two board levels as ground planes, with many vias between them to create a low impedance, high-frequency plane. tie all the device ground pins through multiple vias each to this ground plane, as close to the device as possible. also tie the exposed pad on the bottom of the device to this ground plane. use wide and short traces for the high current paths. the input capacitor should be placed as close as possible to the ic pins as well as the induct or and output capacitor. use a common ground node to minimize the effects of ground noise. table 1. recommended inductors output current inductor value vendor part # comments 600ma 8.2 hcoilcraft mss6122-822mx isl6455 600ma 12 hcoilcraft mss6122-123mx isl6455a table 2. recommended capacitors capacitor value esr/m ? vendor part # comments 10 f<50tdk c2012x5r0j106m ceramic i rms c () o v o 1 v o v i ------- - ? lf ----------------- 1 23 ---------------- - = v o ? v o 1 v o v i ------- - ? lf ----------------- ?? ?? ?? ?? ?? ?? 1 8c o f ------------------------- - esr + ?? ?? = i rms i omax () v o v i ------- - 1 v o v i ------- - ? ?? ?? ?? = vout 0.45 rf ----------- re rf + () = vout1 1.184 rb -------------- - ra rb + () = vout2 1.184 rd -------------- - rc rd + () = isl6455, isl6455a
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9196.0 december 21, 2005 isl6455, isl6455a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l24.4x4b 24 lead quad flat no-lead plastic package (compliant to jedec mo-220vggd-2 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 2.19 2.34 2.49 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 2.19 2.34 2.49 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n242 nd 6 3 ne 6 3 p- -0.609 --129 rev. 0 10/03 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
isl6455a printer friendly version 0.6a pwm regulator and dual 0.3a ldos and reset datasheets, related docs & simulations description key features parametric data application diagrams related devices ordering information part no. design-in status temp. package msl price us $ isl6455aeval1z active eval board n/a isl6455airz active ind 24 ld qfn 2 1.81 ISL6455AIRZ-T5K active ind 24 ld qfn t+r 2 1.81 isl6455airz-tk active ind 24 ld qfn t+r 2 1.81 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the isl6455 is a highly integrated triple output regulator which provides a single chip solution for fpgas and wireless chipset power management. the device integrates a high efficiency synchronous buck regulator (adjustable) with two ultra low noise ldo regulators (adjustable). either the isl6455 or isl6455a can be selected based on whether 3.3v 10% or 5v 10% is required as an input voltage. the synchronous current mode control pwm regulator with integrated n- and p-channel power mosfet provides adjustable voltages based on external resistor setting. synchronous rectification with internal mosfets is used to achieve higher efficiency and reduced number of external components. operating frequency is typically 750khz allowing the use of smaller inductor and capacitor values. the device can be synchronized to an external clock signal in the range of 500khz to 1mhz. the pg_pwm output indicates loss of regulation on pwm output. the isl6455 also has two ldo adjustable regulators using internal pmos transistors as pass devices. ldo2 features ultra low noise typically below 30vrms to aid vco stability. the en_ldo pin controls ldo1 and ldo2 outputs. the isl6455 also integrates a reset function, which eliminates the need for additional reset ic required in wlan and other applications. the ic asserts a reset signal whenever the v in supply voltage drops below a preset threshold, keeping it asserted for at least 25ms after v in has risen above the reset threshold. the pg_ldo output indicates loss of regulation on either of the two ldo outputs. other features include overcurrent protection and thermal shutdown for all the three outputs. high integration and the thin quad flat no-lead (qfn) package makes isl6455 an ideal choice for powering fpgas and small form factor wireless cards such as pcmcia, mini-pci and cardbus-32. key f eatures fully integrated synchronous buck regulator + dual ldo pwm output voltage adjustable. 0.8v to 2.5v with isl6455 (v in = 3.3v) 0.8v to 3.3v with isl6455a (v in = 5.0v) high output current 600ma dual ldo adjustable options ldo1, 1.2v to v in -0.3v (3.3vmax) 300ma ldo2, 1.2v to v in -0.3v (3.3vmax) 300ma ultra-compact dc/dc converter design stable with small ceramic output capacitors and no load high conversion efficiency low shutdown supply current
low dropout voltage for ldos ldo1 150mv (typical) at 300ma ldo2 150mv (typical) at 300ma low output voltage noise <30vrms (typical) for ldo2 (vco supply) pg_ldo and pg_pwm (pwm and ldo) outputs extensive circuit protection and monitoring features pwm overvoltage protection overcurrent protection shutdown thermal shutdown integrated reset output for microprocessor reset proven reference design for total wlan system solution qfn package compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline near chip-scale package footprint improves pcb efficiency and is thinner in profile pb-free plus anneal available (rohs compliant) related documentation application note(s): intersil integrated fet dc/dc converters intersil integrated fet dc/dc converters (simplified chinese) datasheet(s): triple output regulator with single synchronous buck and dual ldo evaluation board(s): isl6455eval1z: 600ma synchronous buck regulator with integrated mosfets i-sim: getting started with isim and isim:pe isl6455a isim java? plug-in setup instructions for windows? 2000 systems parametric data v in (min) (v) 4.5 v in (max) (v) 5.5 v out (min) (v) .8 v out (max) (v) 3.3 i out (max) (a) .6 iq (a) 2500 switching frequency (mhz) .75 peak efficiency (%) 93 por y application block diagrams dvd recorder digital projector fingerprint biometrics iptv set-top box toxic gas monitor applications wlan cards pcmcia, cardbus32, minipci cards compact flash cards hand-held instruments related devices parametric table
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